Choosing the right process is getting to be a difficult step in IC design. That's ironic, because not that long ago the choice of process for a new IC was a no-brainer. You used the most advanced process you could get your hands on to get the benefits of greater integration, higher performance and lower power. Like so much conventional wisdom in the chip business, that ain't necessarily so.
As soon as you try to pin down the selection of a process, the question begins to interact with other variables. For instance, just how much integration do you need? Well, that depends on how much stuff you are trying to cram into the chip, of course. But it also depends on your projected volume. These days, however, it also depends on a second number from marketing—the minimum volume that they can guarantee. If a higher level of integration moves you into a new process that no one on the design team has used before, or that has astonishingly high mask costs or enormous minimum die lots, it may not be justifiable compared with a multichip solution.
Maturity is also an issue. Many design teams who worked with 130-nm foundry processes in 2002 discovered that design rules kept changing during the design, forcing revisions. That led to designer skepticism of announcements that 90-nm processes are now "ready,'' and that the necessary tool chains are in place.
In other cases, claims of improved density, higher performance or lower power can be illusory. Once a design is padlimited, for instance, further decreases in geometry will not necessarily reduce die size. Similarly, once a design is fast enough, it is fast enough. Increased performance can then only be justified by the ability to add more features, or to offer more flexibility to the system developer. And lower power is equally a complex question. Lower dynamic power only translates into lower total power dissipation if duty cycles and static power—a major issue because of leakage current in new processes—are comparable.
But other variables are involved in the process question. One is the range of technologies being integrated. Generally, the more recent the process, the less likely it will be characterized for anything other than digital logic and SRAM. Consequently, it's more likely the responsibility for transistor and interconnect analog modeling will rest with the design team rather than with the foundry. This not only means a significant difference in design costs, but it can inadvertently conceal significant differences in processes as well, such as much lower overall noise margins, problems with passive components or increased on-die process variation with the newer processes.
Such considerations have led some design teams to stay with older processes even at the cost of larger die size or lower-promised-lifetime costs. Others will continue to rely on off-the-shelf components for some critical functions, at least until there is solid proof of a high-volume market. And others will find the security of working with an ASIC vendor to be a wise investment.
Ron Wilson (rwilson@cmp.com) is Editor, Silicon Engineering, for EE Times. He covers the emerging design process for systems-on-chip—from architecture, implementation and flows to test and yield.
