With integration encompassing not just the logic for a communications chip but also the physical-layer (PHY) analog components, a lot of things get more complicated. It's easy to anticipate the design and process problems the analog circuitry will cause. Not so obvious sometimes are the issues that integrated analog creates in testing.
Once you add the high-speed analog circuitry of a PHY to an Ethernet router system-on-chip (SoC), for example, everything gets more complex. To begin with, digital testers have limited analog test capability. So to test the analog components at all will mean adding analog instrumentation to the production test system-often giving up a good part of the test automation in the process. Or it will mean putting the wafer and/or the chip on a separate analog tester, with yield losses due to the additional handling and probing.
Then there's the question of test design. Digital circuitry has two strategies: In functional test you throw input conditions at the chip and observe its behavior until you believe you have put it through all its valid functional sequences. In structural test, you derive a set of inputs that will test the continuity of all the signal paths. The debate rages over which of those is appropriate.
But in the analog world, there isn't really an equivalent. As one sage put it, you don't test analog circuits, you characterize them. When finished testing, you end up with a set of circuit parameters that allow you to drop the die in the right performance bin (or the garbage). That takes time, but analog chips have relatively small pin and component counts.
The situation for an SoC with a half-dozen Ethernet PHY blocks on it is rather different. In the first place, it would take a lot of time to fully characterize all those PHY blocks. Second, it's tricky making sure that each of the blocks is isolated and all its ports brought out to pins without distorting the signals you are trying to measure. Third, a full characterization may be unnecessary if you are just determining if the SoC is working.
Some strategists are leaning toward a kind of functional testing for such integrated mixed-signal chips. Instead of doing a full analog characterization of the transceivers, they are feeding the chip actual communications waveforms and characterizing the performance of the entire PHY blocks. Then, instead of analog measurements of the output of the analog circuitry, they are observing digital results, such as bit error rate, at the digital output. The point is that no one, except failure analysis engineers, really cares how the individual transistors and passives are working: They only want to know if the PHY is usable.
Going one step further: If the PHY turns out to not be within the desired performance envelope, it may be possible to salvage the device by changing filter parameters or even algorithms in the digital signal processing section downstream. Thus the role of test in the analog section changes from merely accepting or rejecting the chip to providing the data with which to tune the digital algorithms.
Ron Wilson (rwilson@cmp.com) is Editor, Silicon Engineering, for EE Times. He covers the emerging design process for systems-on-chip—from architecture, implementation and flows to test and yield.
