Intellectual-property (IP) reuse has been presented to the system-on-chip design community as one of those things, like two hours of exercise and 18 glasses of water a day, that you should do because it's good for you. And generally the discussion remains entirely within the engineering department. It is, after all, about a subject that should be of no interest to marketing—that is, where the blocks that go into a chip come from and how they are applied to the current design. The expected costs of reuse are engineering costs: additional up-front design work on the IP, archiving, tracking and porting overhead, and the costs associated with reusing what you have even when it doesn't quite do what you need. And the claimed benefits apply to engineering: reduced risk, reduced design resources and shorter schedules.
But pressure for design reuse is emerging from outside the engineering department. When market opportunities appear at all these days, they are specific, fleeting and highly cost-sensitive. This new reality is making even skeptics rethink their reuse policies.
A good case in point is the security processor group at Broadcom Corp. (Irvine, Calif.). This group, acquired as BlueSteel Networks in 2000, started out life creating high-speed standalone processor chips for DES, AES and similar encryption algorithms. The processors live in the guts of routers and firewalls to reduce the delays of handling secure links. Like its close competitors in this niche, the Broadcom design group focused on crunching polynomials at very high speeds in order to keep up with packet traffic at what was assumed to be ever-increasing wire speeds.
But the name of the game has changed in two respects, said product-line manager Joseph Wallace. In today's market, the need is to push the product line not to ever-higher speeds but across a wide variety of low to moderate data rates at very low cost. The market wants security processing to be robust, but nearly transparent and nearly free.
You can aim a security processor chip at a particular data rate and system cost. But you have to deliver while that box is under development, or you miss the window. And you have to integrate: The market's approaching price points where box vendors cannot afford to put the security processor on a separate piece of silicon.
The need for different versions of the chip at different price/performance points, and on very short notice, have changed the way the Broadcom team works. It has meant a parallel architecture based on a number of small processors, rather than on one killer core that must be redesigned for each new die size and throughput. The design team can dial in a die size and throughput by selecting the number of processor cores on the die. And to reduce design time, it has become absolutely essential to reuse as much as possible of the core design on each iteration. For the same reasons, it has been essential to reuse the verification suite.
So, there are the virtues of design reuse, stated not as an engineering efficiency but as a market necessity.
Ron Wilson (rwilson@cmp.com) is Editor, Silicon Engineering, for EE Times. He covers the emerging design process for systems-on-chip—from architecture, implementation and flows to test and yield.
