In many ways, the ability to integrate high-speed serial I/O drivers and receivers onto a system-level IC is a godsend. But more often than not, this particular gift is blessed less in the Christian sense of an outright blessing than in the classical Greek notion that it always pays to read the fine print when contracting with the gods.
The benefits, at least, are indisputable. Gigabit serial I/O pins permit large volumes of data to move rapidly between packages without the use of huge numbers of pins on each package. Reduced pin count means less-expensive packaging, less real estate, less complex board layout and, at least potentially, significantly less power lost to interchip communications.
The ability to break a data flow in the middle and route it between packages also means a wonderful new degree of freedom for architects during the system partitioning process. Also, the ability to put the really sophisticated LVDS and similar transceivers on-chip means that systems-on-chip can drive backplanes directly.
All of this is wonderful, of course, until you get to the fine print. Among SoC design teams in the communications field, the integration and verification of high-speed I/O is rapidly emerging as one of the most serious design problems. The most obvious problem is the design of I/O cells that can operate at the required bit rates, in the hundreds of megahertz.
But wait, as they say, there's more. Behind every successful serial I/O pad there lies a very difficult serializer/deserializer (serdes) design. In many cases the design of the serdes and its integration into the surrounding sea of digital logic cells, proves more challenging to the design team than inclusion of the I/O pads. The serdes block may look trivial in Verilog, but it must work with signals at the line rate, has at least some logic functionality, and is farther from the pin than the I/O pad-separated by interconnect, often surrounded by noise sources and farther away from the carefully nurtured I/O supply grid.
To make matters more interesting, most SoCs with high-speed serial I/O have lots of such pins. Designers tend to group LVDS or Rambus I/O pins to form virtual parallel buses, creating enormous throughput-accompanied by enormous design issues.
Experienced design teams have learned that chips with high-speed I/O structures must be floor-planned almost as carefully as microwave chips. Signals must flow onto, across and off the chip over a very orderly, least-distance, least-skew path. Otherwise, timing closure and signal integrity will be nightmares. Power and ground routing becomes a first-order design task, with as many analysis tools as the signal paths use. Decoupling capacitors become vital allies-some design teams design their own capacitor cells to make sure that they can implement all the decoupling they need. And analysis must include not just the on-chip loads, but accurate extracted models of the package and board-signal and supply paths. It's no small challenge.
Ron Wilson is Editor, Silicon Engineering, for EE Times. He covers the emerging design process for systems-on-chip-from architecture, implementation and flows to test and yield. Ron can be reached at rwilson@cmp.com.
