By Fred Olsson and Chris Steele, Cortina Systems
CommsDesign Jun 26, 2007

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Building higher-density network equipment that supports a broader range of data rates requires developing higher-performance packet interconnects. In the past, components with gigabit-scale throughput traditionally have data buses running about 100 Mbits/s per pin. A few years back, differential signaling technology increased this bandwidth about eight times, to about 800 Mbits/s per pin pair, which enables components with throughputs on the order of 10 Gbits/s. One implementation of this technology is System Packet Interface Level 4, Phase 2, or SPI4.2.

Now, new serial technology with clock and data recovery circuitry has again multiplied bandwidth about eight times to about 6 Gbits/s per pin pair, which enables components with many streams of 10 Gbits/s or faster. This article discusses the Interlaken protocol, a new chip-to-chip data transfer protocol that takes advantage of the latest serial technology to multiply the bandwidth performance and density of communications equipment.

The Interlaken protocol is a high-speed, robust, versatile interface for packet transfers between components within communications systems. Interlaken is designed for 10 Gbits/s to 100 Gbits/s inter-chip connectivity. This wide range makes it suitable for many applications and allows generations of devices to be backward-compatible. Sample applications include Ethernet controllers with many 10 Gbits/s ports, OC-768 SONET framers, next-generation 100 Gbits/s Ethernet integrated circuits (ICs), switch fabrics and packet processors.

Interface size
The number of I/O pins in an interface is a significant consideration in new designs. For example, a design for a typical 20 Gbits/s device uses two SPI4.2 interfaces running in parallel. This approach requires more than 160 signal I/O pins and circuit board traces for a bi-directional interface, which adds cost to both the component and the board. An Interlaken interface can provide the same 20 Gbits/s throughput with just 16 I/O pins, using just four bi-directional serializer/deserializer (SerDes) lanes running at 6.25 Gbits/s. Figure 1 highlights the reduction in I/O pins and traces for some typical component bandwidths.