Recent developments in the networking and silicon markets are driving the support of multiple ports of 10 Gigabit Ethernet to the limit. High levels of integration dictate that large numbers of XAUI interfaces must be integrated in silicon to a level where silicon devices are bound by their external interface limitations rather then their internal bandwidth.
In order to minimize the number of SerDes lanes, higher speed lanes are required. The options available today are 6.25Gbps and 10Gbps (XFI) lanes. This article argues that there is a strong business case for DDR-XAUI, a two lane 6.25Gbps XAUI in addition to XFI.
XAUI is an important compatibility interface for 10 Gigabit Ethernet component and system implementers. It provides the low pin-count and long board trace lengths that system vendors need to drive down port costs.
XAUI supports 10Gbps by using four SerDes 3.125Gbps lanes, each lane encoding data with an 8B/10B code. XAUI reduces 10 Gigabit Ethernet's 72 pin XGMII to 16 pins, enabling higher density and lower cost switching chips and optical transceivers. The lower pin count and longer trace lengths allow a single chip to support multiple 10 Gigabit Ethernet ports.
Case Study of High Density 10Gbps Devices
Recently, there has been intense discussion in the IEEE, and the industry as a whole, surrounding the support of 100 Gigabit Ethernet. Even if the support of 100 Gbps as a single port will not materialize in the immediate future due to limitations of the physical layer - one can expect that ASIC solutions supporting bandwidth in excess of 100Gbps, integrating multiple 10 Gbps, will be available soon.
As shown in Figure 1, a device supporting 10 ports of 10Gbps requires 10 interfaces of 10G on the line side (connecting to PHY, MACs, NP, etc.). Towards the system side, the device requires an interface supporting at least a 100 Gbps of bandwidth, and preferably even more to provide some speedup. Although there is an effort to standardize a system side interface for such rates, it is safe to assume that in many implementations XAUI (or enhanced XAUI models) is to be used on the system side as well. Assuming XAUI is used on both ingress and egress, this amounts to a total of at least 80 bi-directional SerDes lanes (10 x 4 + 10 x 4) per device. Considering that some of these devices require external memories for lookup, buffering and other functionalities, the interface limits are crossed.
This limitation grows as the level of functional integration grows. Upcoming high-speed ICs are expected to integrate more of the line card functionality, introducing increasingly more demands of the already exhausted interfaces.
