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05 September 2010



SIGNAL CHAIN BASICS #40: Frequency planning with high-speed ADCs to improve in-band system SFDR

Understand how and why multicarrier ADCs must withstand large signals without reducing sensitivity to small, wanted signals

By Robert Keller,
Systems and Applications Manager,
Texas Instruments

Courtesy of Planet Analog
Apr 05, 2010
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(Editor's note: click here for a complete, linked list of all previous installments of the Signal Chain Basics series.)

With the increasing number of wireless devices, robust radio receivers must reliably receive small signals in the presence of large interfering signals or blockers. Previous generations of radio receivers were designed to receive only one user signal or carrier frequency. The blockers could be attenuated easily in the radio signal chain by analog filtering with a surface acoustic wave (SAW) or other filter after down conversion to an IF frequency.

In newer-generation radios, multicarrier radios that digitize a substantial part—or even the entire RF cellular band—are being developed to drastically save cost and power. Here, there is no opportunity to remove blockers that fall in the digitized band. Therefore, the analog-to-digital converter (ADC) must be able to withstand large signals without reducing sensitivity to small, wanted signals.

The key ADC specification that determines its ability to prevent interference from large signals is spurious free dynamic range (SFDR). This is the ratio in dB of an input tone to the highest spurious signal in the entire output spectrum generated by the tone. Spurious signals generated in the ADC usually result from harmonic distortion, and are usually limited by low-order harmonics like the second or third harmonic.

The SFDR specification by itself does not contain information on the location of the spurious signals generated in the ADC. However, the frequency of harmonics in the output spectrum is deterministic, and based on the harmonic order, input signal frequency, and sample clock frequency. The only difficulty is to realize that harmonic frequencies that fall above the ADC's first Nyquist zone (0 to Fclk/2) will alias back to the Nyquist zone at the ADC output.

The deterministic behavior of harmonic frequencies can be exploited by limiting the signal bandwidth entering the ADC, and choosing the proper input frequency. By eliminating the low-order harmonics, the in band SFDR (the largest spurious signal that falls in the band of interest) can improve as much as 10-20 dB, compared to SFDR across the entire ADC output spectrum.

Texas Instruments provides a simple spreadsheet for calculating the signal band frequency and harmonics up to HD9 at the ADC output (Reference 1).

For example, consider sampling a 25 MHz wanted signal band using TI's ADS4149 14-bit, 250-MSPS converter at Fclk = 250 MHz, and a center IF of 296 MHz. Assume that the 25-MHz signal band is isolated before input in the ADC by a filter with a 4-MHz transition bandwidth (33 MHz total bandwidth), which is reasonable for SAW filter technology.

Inside the filter band, both wanted and blocker signals will pass unattenuated—the wanted signals are located only in the middle 25 MHz of the filter passband, and the blocker signals are assumed to be located anywhere within the 33 MHz of the filter passband and transition band. Outside the 33-MHz filter bandwidth, the interfering signals will be sufficiently attenuated to not generate any harmonics of significant amplitude.

Table 1 lists the inputs for this example (in MHz).


Table 1: Spreadsheet inputs

The frequency bands for wanted signal and HD2-9 at the ADC output are shown in Figure 1. The wanted band covers a frequency band of 33.5–58.5 MHz. The frequency range of both HD2 and HD3 fall only above 59 MHz. Therefore, they will not interfere with any signal in the wanted band.


Figure 1: ADC output frequency bands of wanted signal and HD2-9.
(Click on image to enlarge)

What is the impact of excluding HD2 and HD3? Looking at the ADS4149 datasheet, the SFDR with HD2 and HD3 at 300 MHz IF is 75 dBc, while SFDR excluding HD2 and HD3 is 88 dBc, or a 13-dB improvement. This would allow a system limited by the ADC SFDR to potentially receive signals at a distance of two to three times or more, when compared to a system without frequency planning needed to exclude HD2 and HD3 from overlapping the wanted signals at the ADC output.

Please join us next month when we will talk about clock jitter.

Reference

  1. Spreadsheet for calculating the signal band frequency and harmonics, http://focus.ti.com/docs/toolsw/folders/print/adc-harmonic-calc.html.

About the Author

Robert Keller is the Systems and Applications Manager for High-Speed Data Converters. He has nine years experience supporting high-speed products in wireless infrastructure communication, test and measurement and military systems. He received a B.A. in Physics and Mathematics from Washington University, St. Louis, Missouri, and a Ph.D. in Applied Physics from Stanford University. He has ten US patents in networking and sensor applications.




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